Interconnect Centric High Level Synthesis for Enhanced Layouts with Reduced Wire Length

In Deep Sub-Micron (DSM) technologies, the interconnect significantly impacts the design performance and reliability: a considerable fraction of the total circuit power is consumed by interconnects, crossing the global interconnects requires multiple clock cycles and the wire capacitance directly affects the noise levels. This paper introduces a novel High-Level Synthesis (HLS) methodology that exploits architectural optimizations that lead to final circuits (layouts) with enhanced interconnect power and delay without introducing any overhead. We present a new interconnect-centric scheduling algorithm and a global binding that combines the functional unit binding and register binding. These routines generate circuits with improved interconnect through minimizing the nets (the number and fan-out) and steering logic. The binding process achieves this by considering clusters of operations as compatible candidates instead of individual operations, while the scheduling makes assignments that maximize the cluster compatibility.