Design of a novel low-latency parameterizable posit adder/subtractor using leading one predictor in FPGA

Posit arithmetic has attracted a lot of attention as a promising alternative to the IEEE754 floating-point number representation thanks to its advantages such as higher accuracy and dynamic range. However, hardware solutions are not yet mature, as the posit number representation is still in its infancy. Therefore, posit units are more expensive and low performance than IEEE754 floating-point units. In this paper, a parameterizable low-latency posit adder/subtractor architecture is proposed, which contributes to higher performance posit arithmetic units. Normalization, which is quite slow in standard posit adder/subtractor architectures, is accelerated. The leadingone prediction algorithm is used to determine the amount of left shift required for normalization which reduces the delay time by shortening the critical path. Proposed and standard posit adder/subtractor architectures are implemented on Xilinx Zynq 7000 SoC XC7Z020-CLG484-1 chip with exponent bit length 1, 2, 3 and 4 and precision 16, 32, 64 and 128. The proposed adder/subtractor architecture has lower delay time than the standard architecture at 32, 64 and 128 bits. The results show that the proposed posit adder/subtractor has a lower delay time than the standard design by 0.417 ns, 0.398 ns and 2.636 ns for 32, 64 and 128 bits precision, respectively.

Journal

DIGITAL SIGNAL PROCESSING

Year

2024

Volume

155

ISSN

1051-2004

eISSN

1095-4333

DOI

10.1016/j.dsp.2024.104718

WoS UID

WOS:001295753000001